☑ MCQ PRACTICE

Computer Organization and Architecture Unit 4

Practice objective questions for quick revision and examination preparation. Try answering each question before revealing the answer.

📚 Computer Organization and Architecture
📖 Unit 4
🎯 MCQs

Computer Organization and Architecture - Unit-4

1
In memory-mapped I/O ____________
AThe I/O devices and the memory share the same address space
BThe I/O devices have a separate address space
CThe memory and I/O devices have an associated address space
DA part of the memory is specifically set aside for the I/O operation
Correct Answer The I/O devices and the memory share the same address space
2
The advantage of I/O mapped devices over memory mapped is:
AThe former offers faster transfer of data
BThe devices connected using I/O mapping have a bigger buffer space
CThe devices have to deal with fewer address lines
DNo advantage as such
Correct Answer The devices have to deal with fewer address lines
3
To overcome the lag in the operating speeds of the I/O device and the processor, we use:
ABuffer spaces
BStatus flags
CInterrupt signals
DExceptions
Correct Answer Status flags
4
The method which offers higher speeds of I/O transfers is:
AInterrupts
BMemory mapping
CProgram-controlled I/O
DDMA
Correct Answer DMA
5
The process wherein the processor constantly checks the status flags is called:
APolling
BInspection
CReviewing
DEchoing
Correct Answer Polling
6
The process that periodically checks the status of I/O devices is known as:
ACold swapping
BI/O instructions
CPolling
DDealing
Correct Answer Polling
7
A unit on the bus that initiates bus requests is called:
ASlave
BController master
CStriping
DBus master
Correct Answer Bus master
8
A scheme in which portions of I/O address space are given to I/O devices is called:
AData mapped
BMemory-mapped I/O
CBackplane
DBoth a and b
Correct Answer Both a and b
9
The DMA differs from the interrupt mode by:
AThe involvement of the processor for the operation
BThe method of accessing the I/O devices
CThe amount of data transfer possible
DNone of the mentioned
Correct Answer None of the mentioned
10
The DMA transfers are performed by a control circuit called:
ADevice interface
BDMA controller
CData controller
DOverlooker
Correct Answer DMA controller
11
In DMA transfers, the required signals and addresses are given by the:
AProcessor
BDevice drivers
CDMA controllers
DThe program itself
Correct Answer DMA controllers
12
After the completion of the DMA transfer, the processor is notified by:
AAcknowledge signal
BInterrupt signal
CWMFC signal
DNone of the mentioned
Correct Answer Interrupt signal
13
The DMA controller has _______ registers.
A4
B2
C3
D1
Correct Answer 3
14
When the R/W bit of the status register of the DMA controller is set to 1:
ARead operation is performed
BWrite operation is performed
CRead & Write operation is performed
DNone of the mentioned
Correct Answer Read operation is performed
15
The controller is connected to the ____.
AProcessor bus
BSystem bus
CExternal bus
DNone of the mentioned
Correct Answer System bus
16
Can a single DMA controller perform operations on two different disks simultaneously?
ATrue
BFalse
CMay be
DNone of the above
Correct Answer True
17
The technique whereby the DMA controller steals the access cycles of the processor to operate is called:
AFast conning
BMemory Con
CCycle stealing
DMemory stealing
Correct Answer Cycle stealing
18
The technique where the controller is given complete access to main memory is ________________________.
ACycle stealing
BMemory stealing
CMemory Con
DBurst mode
Correct Answer Burst mode
19
The controller uses _____ to help with the transfers when handling network interfaces.
AInput buffer storage
BSignal enhancers
CBridge circuits
DAll of the mentioned
Correct Answer Input buffer storage
20
To overcome the conflict over the possession of the bus, we use ______.
AOptimizers
BBus arbitrators
CMultiple bus structure
DNone of the mentioned
Correct Answer Bus arbitrators
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