Computer Organization and Architecture - Unit-5
AMultiple bus
BBus arbitrator
CPriority access
DNone of the mentioned
Correct Answer
Bus arbitrator
ABus master
BProcessor
CBus arbitrator
DController
Correct Answer
Bus master
ACentralised arbitration
BDistributed arbitration
CRandom arbitration
DAll of the mentioned
Correct Answer
Centralised arbitration
AOpen-collector
BEX-OR circuit
COpen-drain
DNAND circuit
Correct Answer
Open-drain
APriority
BParallel
CSingle
DDaisy chain
Correct Answer
Daisy chain
AAcknowledge signal
BBus grant signal
CResponse signal
DNone of the mentioned
Correct Answer
Bus grant signal
AProcessor
BDMA controller
CDevice
DBoth Processor and DMA controller
Correct Answer
Both Processor and DMA controller
AIt activates the bus busy line
BPerforms the required operation
CRaises an interrupt
DAll of the mentioned
Correct Answer
It activates the bus busy line
AOpen-drain circuit
BOpen-collector circuit
CEX-OR circuit
DNOR circuit
Correct Answer
Open-collector circuit
AAnother device
BProcessor
CController
DNone of the mentioned
Correct Answer
Processor
ATo indicate the processor is busy
BTo indicate that the bus master is busy
CTo indicate the bus is already allocated
DNone of the mentioned
Correct Answer
To indicate the bus is already allocated
ABus master
BProcessor
CArbitrator
D4-bit ID
Correct Answer
4-bit ID
AAsserts the Start arbitration signal
BSends an interrupt signal
CSends an acknowledge signal
DNone of the mentioned
Correct Answer
Asserts the Start arbitration signal
ABy NANDing the signals passed on all the 4 lines
BBy ANDing the signals passed on all the 4 lines
CBy ORing the signals passed on all the 4 lines
DNone of the mentioned
Correct Answer
By ORing the signals passed on all the 4 lines
ADevice A
BDevice B
CInsufficient information
DNone of the mentioned
Correct Answer
Device B
AUtility software
BSpeed up utilities
COptimizing compilers
DNone of the mentioned
Correct Answer
Optimizing compilers
ASuperscalar operation
BAssembly line operation
CVon Neumann cycle
DNone of the mentioned
Correct Answer
Assembly line operation
AModification in processor architecture
BClock
CSpecial unit
DControl unit
Correct Answer
Clock
Correct Answer
1
ATrue
BFalse
CEither True or False
DNone of the above
Correct Answer
False