☑ MCQ PRACTICE

Computer Organization and Architecture Unit 5

Practice objective questions for quick revision and examination preparation. Try answering each question before revealing the answer.

📚 Computer Organization and Architecture
📖 Unit 5
🎯 MCQs

Computer Organization and Architecture - Unit-5

1
To resolve the clash over the access of the system bus, we use ______.
AMultiple bus
BBus arbitrator
CPriority access
DNone of the mentioned
Correct Answer Bus arbitrator
2
The device which is allowed to initiate data transfers on the bus at any time is called _____.
ABus master
BProcessor
CBus arbitrator
DController
Correct Answer Bus master
3
______ bus arbitration approach uses the involvement of the processor.
ACentralised arbitration
BDistributed arbitration
CRandom arbitration
DAll of the mentioned
Correct Answer Centralised arbitration
4
The circuit used for the request line is a _________.
AOpen-collector
BEX-OR circuit
COpen-drain
DNAND circuit
Correct Answer Open-drain
5
The Centralised bus arbitration is similar to ______ interrupt circuit.
APriority
BParallel
CSingle
DDaisy chain
Correct Answer Daisy chain
6
When the processor receives the request from a device, it responds by sending _____.
AAcknowledge signal
BBus grant signal
CResponse signal
DNone of the mentioned
Correct Answer Bus grant signal
7
In Centralised arbitration, ______ is/are the bus master.
AProcessor
BDMA controller
CDevice
DBoth Processor and DMA controller
Correct Answer Both Processor and DMA controller
8
Once the bus is granted to a device ___________.
AIt activates the bus busy line
BPerforms the required operation
CRaises an interrupt
DAll of the mentioned
Correct Answer It activates the bus busy line
9
The bus busy line is made of ________.
AOpen-drain circuit
BOpen-collector circuit
CEX-OR circuit
DNOR circuit
Correct Answer Open-collector circuit
10
After the device completes its operation, _____ assumes the control of the bus.
AAnother device
BProcessor
CController
DNone of the mentioned
Correct Answer Processor
11
The bus busy line is used:
ATo indicate the processor is busy
BTo indicate that the bus master is busy
CTo indicate the bus is already allocated
DNone of the mentioned
Correct Answer To indicate the bus is already allocated
12
Distributed arbitration makes use of ______.
ABus master
BProcessor
CArbitrator
D4-bit ID
Correct Answer 4-bit ID
13
In Distributed arbitration, the device requesting the bus ______.
AAsserts the Start arbitration signal
BSends an interrupt signal
CSends an acknowledge signal
DNone of the mentioned
Correct Answer Asserts the Start arbitration signal
14
How is a device selected in Distributed arbitration?
ABy NANDing the signals passed on all the 4 lines
BBy ANDing the signals passed on all the 4 lines
CBy ORing the signals passed on all the 4 lines
DNone of the mentioned
Correct Answer By ORing the signals passed on all the 4 lines
15
If two devices A and B contesting for the bus have IDs 5 and 6 respectively, which device gets the bus based on Distributed arbitration?
ADevice A
BDevice B
CInsufficient information
DNone of the mentioned
Correct Answer Device B
16
______ have been developed specifically for pipelined systems.
AUtility software
BSpeed up utilities
COptimizing compilers
DNone of the mentioned
Correct Answer Optimizing compilers
17
The pipelining process is also called ______.
ASuperscalar operation
BAssembly line operation
CVon Neumann cycle
DNone of the mentioned
Correct Answer Assembly line operation
18
The fetch and execution cycles are interleaved with the help of ________.
AModification in processor architecture
BClock
CSpecial unit
DControl unit
Correct Answer Clock
19
Each stage in pipelining should be completed within ____ cycle.
A1
B2
C3
D4
Correct Answer 1
20
In pipelining, the task which requires the least time is performed first.
ATrue
BFalse
CEither True or False
DNone of the above
Correct Answer False
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