1.In memory-mapped I/O ____________

A . The I/O devices and the memory share the same address space

B . The I/O devices have a seperate address space

C . The memory and I/O devices have an associated address space

D . A part of the memory is specifically set aside for the I/O operation

Answer

2. The advantage of I/O mapped devices to memory mapped is

A . The former offers faster transfer of data

B . The devices connected using I/O mapping have a bigger buffer space

C . The devices have to deal with fewer address lines

D . No advantage as such

Answer

3.To overcome the lag in the operating speeds of the I/O device and the processor we use

A . BUffer spaces

B . Status flags

C . Interrupt signals

D . Exceptions

Answer

4.The method which offers higher speeds of I/O transfers is

A . Interrupts

B . Memory mapping

C . Program-controlled I/O

D . DMA

Answer

5.The process where in the processor constantly checks the status flags is called as

A . Polling

B . Inspection

C . Reviewing

D . Echoing

Answer

6.Process that periodically checks status of an I/O devices, is known as

A . Cold swapping

B . I/O instructions

C . Polling

D . Dealing

Answer

7.A unit on bus that initiates bus requests is called

A . Slave

B . Controller master

C . Striping

D . Bus master

Answer

8. A scheme in which portions of I/O address space are given to I/O devices, is called

A . Data mapped

B . Memory-mapped I/O

C . Backplane

D . both a and b

Answer

9.The DMA differs from the interrupt mode by

A . The involvement of the processor for the operation

B . The method accessing the I/O devices

C . The amount of data transfer possible

D . None of the mentioned

Answer

10..The DMA transfers are performed by a control circuit called as

A . Device interface

B . DMA controller

C . Data controller

D . Overlooker

Answer

11.. In DMA transfers, the required signals and addresses are given by the

A . Processor

B . Device drivers

C . DMA controllers

D . The program itself

Answer

12.. After the completion of the DMA transfer the processor is notified by

A . Acknowledge signal

B . Interrupt signal

C . WMFC signal

D . None of the mentioned

Answer

13..The DMA controller has _______ registers

A . 4

B . 2

C . 3

D . 1

Answer

14.. When the R/W bit of the status register of the DMA controller is set to 1.

A . Read operation is performed

B . Write operation is performed

C . Read & Write operation is performed

D . None of the mentioned

Answer

15..The controller is connected to the ____

A . Processor BUS

B . System BUS

C . External BUS

D . None of the mentioned

Answer

16..Can a single DMA controller perform operations on two different disks simulteneously?

A . True

B . False

C . May be

D . None of the above

Answer

17..The techinique whereby the DMA controller steals the access cycles of the processor to operate is called

A . Fast conning

B . Memory Con

C . Cycle stealing

D . Memory stealing

Answer

18..The technique where the controller is given complete access to main memory is________________________

A . Cycle stealing

B . Memory stealing

C . Memory Con

D . Burst mode

Answer

19.. The controller uses _____ to help with the transfers when handling network interfaces.

A . Input Buffer storage

B . Signal echancers

C . Bridge circuits

D . All of the mentioned

Answer

20..To overcome the conflict over the possession of the BUS we use ______

A . Optimizers

B . BUS arbitrators

C . Multiple BUS structure

D . None of the mentioned

Answer

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☞ Computer Organization and Architecture (COA) Objective Question Bank-Unit-1 - [ COA ]

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