1.To resolve the clash over the access of the system BUS we use ______

A . Multiple BUS

B . BUS arbitrator

C . Priority access

D . None of the mentioned

Answer

2.The device which is allowed to initiate data transfers on the BUS at any time is called _____

A . BUS master

B . Processor

C . BUS arbitrator

D . Controller

Answer

3.______ BUS arbitration appproach uses the involvement of the processor

A . Centralised arbitration

B . Distributed arbitration

C . Random arbitration

D . All of the mentioned

Answer

4.The circuit used for the request line is a _________

A . Open-collector

B . EX-OR circuit

C . Open-drain

D . Nand circuit

Answer

5.The Centralised BUS arbitration is similar to ______ interrupt circuit

A . Priority

B . Parallel

C . Single

D . Daisy chain

Answer

6. When the processor recieves the request from a device, it responds by sending _____

A . Acknowledge signal

B . BUS grant signal

C . Response signal

D . None of the mentioned

Answer

7. In Centralised Arbitration ______ is/are is the BUS master

A . Processor

B . DMA controller

C . Device

D . Both Processor and DMA controller

Answer

8. Once the BUS is granted to a device ___________

A . It activates the BUS busy line

B . Performs the required operation

C . Raises an interrupt

D . All of the mentioned

Answer

9. The BUS busy line is made of ________

A . Open-drain circuit

B . Open-collector circuit

C . EX-Or circuit

D . Nor circuit

Answer

10.. After the device completes its operation _____ assumes the control of the BUS.

A . Another device

B . Processor

C . Controller

D . None of the mentioned

Answer

11.. The BUS busy line is used

A . To indicate the processor is busy

B . To indicate that the BUS master is busy

C . To indiacate the BUS is already allocated

D . None of the mentioned

Answer

12.. Distributed arbitration makes use of ______

A . BUS master

B . Processor

C . Arbitrator

D . 4-bit ID

Answer

13.. In Distributed arbitration, the device requesting the BUS ______

A . Asserts the Start arbitration signal

B . Sends an interrupt signal

C . Sends an acknowledge signal

D . None of the mentioned

Answer

14.. How is a device selected in Distributed arbitration?

A . By NANDing the signals passed on all the 4 lines

B . By ANDing the signals passed on all the 4 lines

C . By ORing the signals passed on all the 4 lines

D . None of the mentioned

Answer

15.. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration

A . Device A

B . Device B

C . Insufficient information

D . None of the mentioned

Answer

16.. ______ have been developed specifically for pipelined systems.

A . Utility softwares

B . Speed up utilities

C . Optimizing compilers

D . None of the mentioned

Answer

17.. The pipelining process is also called as ______

A . Superscalar operation

B . Assembly line operation

C . Von Neumann cycle

D . None of the mentioned

Answer

18.. The fetch and execution cycles are interleaved with the help of ________

A . Modification in processor architecture

B . Clock

C . Special unit

D . Control unit

Answer

19.. Each stage in pipelining should be completed within ____ cycle.

A . 1

B . 2

C . 3

D . 4

Answer

20.. In pipelining the task which requires the least time is performed first.

A . True

B . False

C . Either True or False

D . None of the above

Answer

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Relevant Materials :

☞ Computer Organization and Architecture (COA) Objective Question Bank-Unit-1 - [ COA ]

☞ Computer Organization and Architecture (COA) Objective Question Bank-Unit-2 - [ COA ]

☞ Computer Organization and Architecture (COA) Objective Question Bank-Unit-3 - [ COA ]

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