Study Glance
🔢
B.Tech CSE COA (Bloom's Taxonomy Aligned)

Computer Organization and Architecture Important Questions

Unit-wise important 2-mark, 5-mark and 10-mark questions structured across all levels of Bloom's Taxonomy for semester examination preparation.

No questions found Try searching for another topic, unit or question.
Unit I

Digital Logic & Data Representation

Boolean Algebra, Logic Gates, Binary Codes, Data & Floating-Point Representation

2-Mark Questions

10
  1. Define Boolean algebra.
  2. State fundamental logic gates.
  3. List common binary codes used in digital systems.
  4. Identify the purpose of binary storage and registers.
  5. Explain binary logic operations.
  6. Summarize the different data types in digital computers.
  7. Describe the purpose of number complements in digital arithmetic.
  8. Distinguish between fixed-point and floating-point representations.
  9. Demonstrate the conversion of a decimal number into binary using 2s complement.
  10. Apply IEEE floating-point standards to identify sign and exponent fields.

5-Mark Questions

8
  1. Explain Boolean algebra postulates and simplification using algebraic reduction.
  2. Analyze various binary codes including BCD, Excess-3, and Gray code for error detection.
  3. Examine fixed-point number representations (signed magnitude, 1s, and 2s complement).
  4. Explain floating-point number representation format and normalization rules.
  5. Demonstrate how arithmetic operations are performed using complement representations.
  6. Analyze the functional block diagram of a digital computer.
  7. Explain the distinction between computer organization and computer architecture.
  8. Compare universal logic gates (NAND and NOR) with basic gates.

10-Mark Questions

3
  1. Evaluate the trade-offs between fixed-point and floating-point data representations in high-performance computing.
  2. Design a comprehensive digital data representation and arithmetic pipeline for a 32-bit microprocessor architecture.
  3. Formulate an advanced digital logic reduction and code conversion scheme for custom hardware controllers.
Unit II

Combinational & Sequential Circuits

Adders, Multiplexers, Latches, Flip-Flops, Registers & Counters

2-Mark Questions

10
  1. Define a combinational circuit.
  2. State the primary difference between combinational and sequential circuits.
  3. List standard MSI combinational components.
  4. Identify the function of a multiplexer.
  5. Explain the operation of SR and D latches.
  6. Summarize state reduction and assignment in sequential design.
  7. Distinguish between ripple counters and synchronous counters.
  8. Describe the role of Hardware Description Language (HDL).
  9. Demonstrate the truth table for a binary half-adder.
  10. Apply flip-flop characteristic equations to solve excitation states.

5-Mark Questions

8
  1. Explain the analysis and systematic design procedure for combinational circuits.
  2. Analyze the architecture of a 4-bit binary adder-subtractor circuit.
  3. Examine decoder and encoder designs with logic gate implementations.
  4. Explain clocked sequential circuits and flip-flop triggering mechanisms.
  5. Demonstrate how Hardware Description Language (HDL) models combinational logic.
  6. Analyze state tables and state diagrams in sequential machine design.
  7. Explain shift registers and bidirectional parallel load operations.
  8. Compare asynchronous counters with synchronous counter architectures.

10-Mark Questions

3
  1. Evaluate the performance and propagation delay trade-offs between ripple carry adders and carry look-ahead adders.
  2. Design a complete sequential control unit (registers, counters, and state machines) for a digital vending machine or calculator.
  3. Formulate an advanced HDL structural modeling suite for complex arithmetic and logic units.
Unit III

Register Transfer Language & Basic Computer Organization

RTL, Micro-Operations, Bus Transfers, Instruction Codes & Instruction Cycle

2-Mark Questions

10
  1. Define Register Transfer Language (RTL).
  2. State the notation for register transfer operations.
  3. List common computer registers (PC, AC, DR, AR, IR).
  4. Identify the function of a common bus system.
  5. Explain arithmetic micro-operations with examples.
  6. Summarize the phases of an instruction cycle.
  7. Distinguish between memory-reference and register-reference instructions.
  8. Describe the role of timing and control signals.
  9. Demonstrate register transfer statements for a memory read operation.
  10. Apply RTL statements to execute an arithmetic shift micro-operation.

5-Mark Questions

8
  1. Explain Register Transfer Language rules and basic micro-operation categories.
  2. Analyze bus and memory transfers using multiplexers and tristate buffers.
  3. Examine the architecture and design of an Arithmetic Logic Shift Unit (ALSU).
  4. Explain stored program organization and instruction code formats.
  5. Demonstrate the hardware implementation of common computer registers and bus connections.
  6. Analyze the instruction fetch, decode, and execution timing sequence.
  7. Explain input-output instructions and interrupt-handling cycles.
  8. Compare hardwired control unit design with functional requirements.

10-Mark Questions

3
  1. Evaluate the execution efficiency of memory-reference instructions within a single-bus organizational model.
  2. Design a complete micro-operation execution unit and timing diagram for a custom accumulator-based basic computer.
  3. Formulate an optimized instruction set architecture (ISA) routing structure using advanced RTL notation.
Unit IV

Microprogrammed Control, CPU & Computer Arithmetic

Control Memory, Addressing Modes, Instruction Formats & Arithmetic Algorithms

2-Mark Questions

10
  1. Define microprogrammed control.
  2. State the purpose of control memory.
  3. List general CPU register organization structures.
  4. Identify common addressing modes.
  5. Explain address sequencing in control memory.
  6. Summarize Booths multiplication algorithm principle.
  7. Distinguish between restoring and non-restoring division.
  8. Describe floating-point arithmetic operation steps.
  9. Demonstrate effective address calculation using indexed addressing mode.
  10. Apply BCD arithmetic rules for decimal addition.

5-Mark Questions

8
  1. Explain microprogrammed control unit architecture and control address registers.
  2. Analyze CPU instruction formats (zero, one, two, and three address instructions).
  3. Examine various addressing modes with practical examples and execution overhead.
  4. Explain hardware implementation of signed-magnitude binary addition and subtraction.
  5. Demonstrate Booths algorithm for multiplication of signed binary numbers.
  6. Analyze restoring division algorithms and quotient generation steps.
  7. Explain floating-point arithmetic operations and overflow/underflow handling.
  8. Compare hardwired control units with microprogrammed control units.

10-Mark Questions

3
  1. Evaluate the architectural trade-offs between horizontal and vertical microprogrammed control units.
  2. Design a complete CPU arithmetic and logic execution pipeline supporting floating-point operations and Booth multiplication.
  3. Formulate an advanced addressing mode resolution and instruction decoding engine for a RISC/CISC processor.
Unit V

Input-Output & Memory Organization

I/O Interfaces, Asynchronous Transfer, DMA, Memory Hierarchy & Cache Memory

2-Mark Questions

10
  1. Define an input-output interface.
  2. State asynchronous data transfer mechanisms.
  3. List modes of data transfer.
  4. Identify memory hierarchy levels.
  5. Explain strobe control and handshaking.
  6. Summarize priority interrupt configurations (daisy chaining).
  7. Distinguish between direct memory access (DMA) and programmed I/O.
  8. Describe cache memory mapping techniques.
  9. Demonstrate hit ratio calculation for cache memory access.
  10. Apply replacement algorithms (FIFO/LRU) to cache line evictions.

5-Mark Questions

8
  1. Explain peripheral device communication and input-output interface standards.
  2. Analyze asynchronous data transfer protocols using handshaking signals.
  3. Examine priority interrupt mechanisms and parallel priority hardware.
  4. Explain Direct Memory Access (DMA) controller architecture and burst transfers.
  5. Demonstrate how memory hierarchy achieves speed and capacity balance.
  6. Analyze cache memory organization and mapping techniques (direct, associative, set-associative).
  7. Explain associative memory design and match logic circuitry.
  8. Compare main memory RAM/ROM chips with auxiliary storage devices.

10-Mark Questions

3
  1. Evaluate the performance impact of cache mapping policies (write-through vs write-back) on multi-core processor systems.
  2. Design an advanced memory management and DMA controller interface architecture for a high-throughput I/O subsystem.
  3. Formulate a comprehensive memory hierarchy and cache coherence framework for enterprise computing systems.
💡

Exam Preparation Tip

These questions are structured across all levels of Bloom's Taxonomy (Remember, Understand, Apply, Analyze, Evaluate, Create). Begin with 2-mark foundational definitions, progress to 5-mark conceptual analysis and algorithms, and master 10-mark architectural evaluation and design problems.